ÐßÐßÊÓƵ

VLSI Cad and Signal Integrity Laboratory

Lab Director

Doctoral Student  

Sofikul Islam 

Dissertation Title:  "Mitigation of Thermally Induced Soft Errors in VLSI Designs", Graduated in Fall 2017- Currently Physical Design Engineer at Intel Corporation San Jose, California

Thesis Students Graduated

• Pankaj Bhowmik, MSEE, Dec. 2016,Title:“Mitigation of Temperature Induced Single Event Crosstalk Noise”, Currently a Ph.D. student at University of Arkansas
• Bulbul Ahmed, MSEE, Dec. 2016,Title: “Minimization Of Crosstalk, Power Consumption And Inductive Noise In Interconnect”, Currently a Ph.D. student at University of Virginia
• Md. Adnan Zaman, MSEE, Aug 2016, Title: “Analysis and Modeling of Normal Signal Switching Induced Crosstalk Delay and Speedup in Nanometer Technologies”,Currently a Ph.D. student at University of South Florida
• Sujan Kumar Saha, MSEE, Aug 2016, Title: “Minimization of Interconnect Crosstalk Noise and Power Consumption in Nanoscale Designs”,
• Archit Shah, MSEE, May 2016, Title: “3D Analysis of Self-Heating and its Impact on Performance of SOI and Bulk FINFET”.
• Mustafizur Rahman, MSEE, May 2015, Title: “Reduction of Temperature Induced Clock Skew and Crosstalk”.
• Syed A. Rahman, MSEE, May 2015,Title: “Reliability Analysis of Various Body Biasing Techniques”.
• Md A. Sayeed, MSEE, May 2015,Title: “Soft Error Mitigation Using Driver Sizing Combined With Transmission Gate”,Currently Assistant Professor of Electronic Engineering Tech. at Eastern New Mexico University
• Palash Datta, MSEE, May 2014,Title: “Soft error mechanisms in FINFET devices
• Mahgol Sadat Moussavi, MSEE, August 2014,Title: “Comparison of various circuit level power optimization techniques”.
• Kaustubh V. Dhonsale, MSEE, August 2014,Title: “A combine method for soft-error mitigation using DTMOS and varied gate and body bias”. Currently works at “Panasonic Automotive systems”.
• Li Yuan, MSEE, August 2013,Title: “Analysis and Modeling of Single Event Induced Signal Speedup”.
• Yao Yao, MSEE, August 2013,Title: “Predicting Single Event Coupling Delay in Nanometer Technologies”.
• Md. Azharul Islam, MSEE, May 2013,Title: “Transmission Gate Input Voltage Control for Soft Error Mitigation”.
• Partivkumar B. Prajapati, MSEE, May 2011,Title: “A Comparison of Radiation Tolerance of Different Logic Styles”.
• Vinaychawdary Singamaneni, MSEE, August 2011,Title: “Crosstalk Mitigation Using Varying Transmission Gate Voltage”.
• Priyank Nerurkar, MSEE, December 2011,Title: “Radiation Tolerance of Low Power Design Techniques”.
• Harikrushna H. Dhameliya, MSEE, December 2011,Title: “Radiation Induced Soft Error Mechanisms in Nanoscale CMOS”, Works at Reliance Communications Ltd
• Bo Sun, MSEE, December 2011,Title: “Transmission Gate Technique for Soft Error Mitigation in Nanometer CMOS Circuits”,Currently  at “TU Delft Beijing Research Center”
• Juyu Wang, MSEE, May 2010,Title: “Comparison on various Combinational Logic Related Soft Errors”.Currently a Ph.D. student at University of Houston
• Vijay K. Boorla, MSEE, May 2010, Title: “Closed form modeling for Single Event Crosstalk and mitigation techniques”.
• Nareshkumar B. Patel, MSEE, August 2010,Title: “Soft Error Mitigation using Dynamic Threshold”, works at Electromagnetic industries 
• Abhishek Balaji Akkur, MSEE, August 2008,Title: Single Event Crosstalk Noise Contamination in Nanoscale Circuits”, Works as Senior Circuit Design Engineer at NVIDIA, San Jose, California.
• Selcuk Belek, MSEE, August 2008,Title: “High Altitude Simulation of Fuel Cell”,
• Srinivas Achanta, MSEE, August 2008,“Comparison of Circuit Level Hardening Techniques for CMOS Combinational Logic”, Development Lead Engineer at Schweitzer Engineering Laboratories.
• Uday K. Borra, MSEE, December 2007,Title: “An Analytical Model For Crosstalk Delay Estimation In Deep Sub-Micron VLSI Circuits”, Product Development Engineer, Intel Corp, Santa Clara, CA.
• Merlyn Rudrapati, MSEE, December 2006,Title: “An Improved Crosstalk Noise Model for On-Chip Interconnects”.
• Michael Anita, MSEE, May 2005,Title: “An Accurate and Time Efficient Cross-talk Noise Model for Multi-line Circuits and its use in Interconnect Optimization”,Post Silicon Validation Engineer,Intel Corporation, Austin, TX.